The present invention relates generally to electrical circuits and, more particularly, to a system and methodology that mitigates overshoot during power up of an electrical circuit.
Numerous types of electronic devices for a myriad of applications employ electrical circuits implemented as one or more integrated circuits (ICs). For example, ICs can be configured to achieve desired functions, such as, controlling associated devices and elements. For instance, ICs can be utilized to bias magneto resistive (MR) elements for reading and writing data to associated magnetic surface utilized in hard disc drives. However, it is often the case that at power up or during switching, currents or voltages supplied by ICs overshoot or spike above intended values.
By way of further illustration, various types of electronic circuitry, such as current mirrors, are commonly utilized in conjunction with ICs in biasing associated devices or performing current steering functions. A current mirror is fed by a current source, which can be a constant- or variable-current source. The current mirror provides an output current to associated parts of the IC based on the input current. In operation, overshoot tends to occur at a base node of the current mirror, which overshoot can be propagated through current mirrors to various parts of the IC. As a result, a current mirror often exposes sensitive associated circuitry to the risks of overshoot.
These unintended overshooting and undershooting conditions can have deleterious effects on the associated circuitry. The overshooting and undershooting tend to become more problematic with sensitive devices or components. For example, sensitive devices, including MR elements, can experience adverse coupling and/or recovery times if exposed to overshoot conditions, such as tend to occur at power up or fast recovery modes when biasing signals are applied initially.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to a system and method to mitigate overshoot in an IC, such as can occur at power up or activation of associated circuitry. When enabled, such as in response to application power (e.g., at power up), a protection system coupled to a node operates in a protection mode to facilitate a voltage at the node to rise to a desired level and then switches to a normal mode with little or no overshoot. In the normal mode a desired fixed voltage can be supplied to the node, for example. Because overshoot is substantially eliminated, such an approach provides for fast and safe recovery and is generally self-protecting.
A particular aspect of the present invention provides a transistor having a base coupled to the node. The transistor""s base and collector are connected (e.g., diode connecting the transistor) for a period of time so as to mitigate overshoot at the node during start up (power up). The diode connection can be implemented for a predetermined time period or for a time period based on the voltage at the node. The diode connection is then removed and a desired voltage can be safely supplied to the node for normal operation of the associated IC.
Another aspect of the present invention provides a method for protecting a node of associated circuitry from fluctuations; such as tend to occur at power up. The method includes enabling protection of the node, such as in response to application of power to an associated IC. The protection can be implemented, for example, by diode connecting a transistor having its base coupled to the node where protection is desired. After the node reaches the approximate desired ending voltage, the protection is disabled (e.g., removing the diode connection from the transistor) and the node can be connected to the desired ending voltage, such as provided by an associated power supply.
The following description and the annexed drawings set forth certain illustrative aspects of the invention. These aspects are indicative, however, of a few ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.